A conventional trench-gated power MOSFET 10 is shown in the cross-sectional view of FIG. 1. MOSFET 10 is formed in an N+ semiconductor substrate 11, on which an N-epitaxial layer 12 is grown. A gate 13 is formed in a trench 14 which extends downward from the top surface of the N-epitaxial (N-epi) layer 12. The gate is typically made of polycrystalline silicon (polysilicon) and is electrically isolated from the N-epi layer 12 by an oxide layer 15. The voltage applied to the gate 13 controls the current flowing between an N+ source 16 and a drain 18, through a channel located adjacent the wall of the trench 14 in a P-body 17. Drain 18 includes the N-epi layer 12 and N+ substrate 11. A metal contact layer 19 makes electrical contact with the N+ source 16 and with the P-body 17 through a P+ body contact region 20. A similar metal contact layer (not shown) typically provides an electrical connection with the bottom side of the drain 18.
Ideally, the MOSFET would operate as a perfect switch, with infinite resistance when turned off and zero resistance when turned on. In practice, this goal cannot be achieved, but nonetheless two important measures of the efficiency of the MOSFET are its on-resistance and avalanche breakdown voltage (hereinafter "breakdown voltage"). Another important criterion is where the breakdown occurs. Since the drain is normally biased positive with respect to the source, the junction 21 is reverse-biased, and avalanche breakdown normally occurs at the corner of the trench, where the electric field is at a maximum. Breakdown creates hot carriers which can damage or rupture the gate oxide layer 15. It is therefore desirable to design the device such that breakdown occurs in the bulk silicon, away from the trench 14.
Another important characteristic of a MOSFET is its threshold voltage, which is the voltage that needs to be applied to the gate in order to create an inversion layer in the channel and thereby turn the device on. In many cases it is desirable to have a low threshold voltage, and this requires that the channel region be lightly doped. Lightly doping the channel, however, increases the risk of punchthrough breakdown, which occurs when the depletion region around the junction 21 expands so as to reach all the way across the channel to the source. The depletion region expands more rapidly when the body region is more lightly doped.
One technique for reducing the strength of the electric field at the corners of the trench and promoting breakdown in the bulk silicon away from the trench is taught in U.S. Pat. No. 5,072,266 to Bulucea et al. (the "Bulucea patent") This technique is illustrated in FIG. 2, which shows a MOSFET 25, which is similar in MOSFET 10 of FIG. 1 except that a deep P+ diffusion 27 extends downward from the P-body 17 to a level below the bottom of the trench. Deep P+ diffusion 27 has the effect of shaping the electric field in such a way as to reduce its strength at the corner 29 of the trench.
While the technique of the Bulucea patent improves the breakdown performance of the MOSFET, it sets a lower limit on the cell pitch, shown as "d" in FIG. 2, because if the cell pitch is reduced too much, dopant from the deep P+ diffusion will get into the channel region of the MOSFET and increase its threshold voltage. Reducing the cell pitch increases the total perimeter of the cells of the MOSFET, providing a greater gate width for the current, and thereby reduces the on-resistance of the MOSFET. Thus, the net effect of using the technique of the Bulucea patent to improve the breakdown characteristics of the MOSFET is that it becomes more difficult to reduce the on-resistance of the MOSFET.
To summarize, the design of a power MOSFET requires that a compromise be made between the threshold and breakdown voltages and between the on-resistance and breakdown characteristics of the device. There is thus a clear need for a MOSFET structure that avoids or minimizes these compromises without adding undue complexity to the fabrication process.